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wishbone master puzzle by ureyhu1 on Jul 9, 2010			ureyhu1 Posts: 3 Joined: May 7, 2010 Last seen: Jul 20, 2010
Hello everybody: I'm fresh to the Wishbone Bus. However in my current project,I have to implement a wishbone master port to fetch data from memory and process , rewrite it through bus.But I was stuck. I am thinkking about is there some example explain the master port.(The wishbone specification only list some wishbone slave examples.) Thanks any way. Hello everybody: I'm fresh to the Wishbone Bus. However in my current project,I have to implement a wishbone master port to fetch data from memory and process , rewrite it through bus.But I was stuck. I am thinkking about is there some example explain the master port.(The wishbone specification only list some wishbone slave examples.) Thanks any way.

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